In the prior art, there are microprocessors, microcomputers and other data processors and computers which have addressable special registers. Typically such registers have a uniform length that is compatible with the width of a data bus included in the particular system. There are reasons, such as for increasing the facility for manipulating address information contained in special registers, that the uniform length constraint should be removed. Then arithmetic and logical manipulation of address information may be accomplished on data words which are longer than the width of the data bus. To accomplish such manipulation of longer data words, plural consecutive addresses are used to define the location of the special registers.
There are arrangements, such as direct memory access circuits, in the prior art for generating plural consecutive addresses from an initial address. A general description of a direct memory access arrangement is presented by A. Osborne in An Introduction to Microcomputers Vol. 1, 1976, pages 5-34 to 5-41. The initial address is loaded into an address register and is automatically incremented a number of times. Each time it is incremented it is used to address another part of the data. The number of times that the address is incremented is determined by reference to another piece of information which represents the number. This number is decremented each time the address is incremented. When the number is decremented to zero, the process of sequential address generation is terminated.
The foregoing requires the attention of the programmer to insert the appropriate number of times to increment the address in his program in association with every occurrence of the address of a special register.
For applications wherein access to such special registers occurs often during programming, it is convenient to relieve the programmer of this task.